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論文 (査読有り)

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  1. D. Suzuki, T. Oka, A. Tamakoshi, Y. Takako, and T. Hanyu, ``Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator," Jpn. J. Appl. Phys., vol. 61, Apr. 2022 (to be published).
  2. D. Suzuki, T. Oka, A. Tamakoshi, Y. Takako, and T. Hanyu, ``Design Framework for an Energy-Efficient Binary Convolutional Neural Network Accelerator Based on Nonvolatile Logic," Nonlinear Theory and Its Applications (NOLTA), vol. 12, no. 4, pp. 695-710, Oct. 2021.
  3. D. Suzuki and T. Hanyu, ``Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow," IEICE Trans. Inf. & Syst., vol. E104-D, no. 8, pp. 1111-1120, Aug. 2021.
  4. D. Suzuki, T. Oka, and T. Hanyu, ``Design of an Energy-Efficient Binarized Convolutional Neural Network Accelerator Using a Nonvolatile Field-Programmable Gate Array with Only-Once-Write Shifting" Jpn. J. Appl. Phys., vol. 60, pp. SBBB07~1-SBBB07~9, Apr. 2021.
  5. D. Suzuki and T. Hanyu, ``Design of a Cost-Efficient Controller for Realizing a Data-Shift-Minimized Nonvolatile Field-Programmable Gate Array," Jpn. J. Appl. Phys., vol. 59, no. SG, pp. SGGB13~1-SGGB13~7, Apr. 2020.
  6. M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu, ``A 47.14μW 200MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications," IEEE J. Solid State Circuits (JSSC), vol. 54, No. 11, pp. 2991-3004, Aug. 2019.
  7. D. Suzuki and T. Hanyu, ``Design of a Highly Reliable, High-Speed MTJ-Based Lookup Table Circuit Using Fractured Logic-in-Memory Structure," Jpn. J. Appl. Phys. (JJAP), vol. 58, No. SB, pp. SBBB10~1-SBBB10~7, Apr. 2019.
  8. D. Suzuki, T. Oka, and T. Hanyu, ``Circuit Optimization Technique of Nonvolatile Logic-In-Memory Based Lookup Table Circuits Using Magnetic Tunnel Junction Devices," Microelectronics Journal, Vol. 83, pp. 39-49, Jan. 2019.
  9. D. Suzuki and T. Hanyu, ``Design of a Magnetic-Tunnel-Junction-Oriented Nonvolatile Lookup Table Circuit with Write-Operation-Minimized Data Shifting," Jpn. J. Appl. Phys. (JJAP), vol. 57, No. 4S, pp. 04FE09~1-04FE09~4, Mar. 2018.
  10. D. Suzuki and T. Hanyu, ``Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme," IEICE Trans. Inf. & Syst., vol. E100-D, No. 8, pp. 1618-1624, Aug. 2017.
  11. D. Suzuki and T. Hanyu, ``Design of a Low-Power Nonvolatile Flip-Flop Using 3-Terminal Magnetic-Tunnel-Junction-Based Self-Terminated Mechanism," Jpn. J. Appl. Phys. (JJAP), vol. 56, No. 4S, pp. 04CN06~1-04CN06~5, Mar. 2017.
  12. D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, ``Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications," Institute of Engineering Technology (IET), Electronics Letters, vol. 53, No. 7, pp. 456-458, Mar. 2017.
  13. T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno, ``Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing," Proc. IEEE, vol. 104, No. 10, pp. 1844-1863, Oct. 2016.
  14. D. Suzuki and T. Hanyu, ``Nonvolatile Field-Programmable Gate Array Using 2-Transistor-1-Magnetic-Tunnel-Junction-Vell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic," Jpn. J. Appl. Phys. (JJAP), vol. 54, No. 4S, pp. 04DE01~1-04DE01~5, Mar. 2015.
  15. M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, ``Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction," IEEE J. Solid-State Circuits (JSSC), vol. 50, No. 2, pp. 476-489, Feb. 2015.
  16. D. Suzuki and T. Hanyu, ``Magnetic-Tunnel-Junction Based Low-Energy Nonvolatile Flip-Flop Using An Area-Efficient Self-Terminated Write Driver," J. Appl. Phys. (JAP), vol. 117, pp. 17B504~1-17B504~3, Jan. 2015.
  17. D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, ``Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic," IEEE Trans. Magn., vol. 50, No. 11, pp. 3402104~1-3402104~4, Nov. 2014.
  18. D. Suzuki, N. Sakimura, M. Natsui, A. Mochizuki, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, ``A Compact Low-Power Nonvolatile Flip-Flop Using Domain-Wall-Motion-Device-Based Single-Ended Structure," IEICE Electronics Express (ELEX), vol. 11, No. 13, pp. 20140296~1-20140296~11, June 2014.
  19. D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, ``Design and Fabrication of a Perpendicular Magnetic Tunnel Junction Based Nonvolatile Programmable Switch Achieving 40% Less Area Using Shared-Control Transistor Structure," J. Appl. Phys. (JAP), vol. 115, No. 17, pp. 17B742-1-17B742-3, Mar. 2014.
  20. D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, ``Design and Evaluation of a 67% Area-Less 64-Bit Parallel Reconfigurable 6-Input Nonvolatile Logic Element Using Domain-Wall Motion Devices," Jpn. J. Appl. Phys. (JJAP), vol. 53, No. 4S, pp. 04EM03~1-04EM03~5, Feb. 2014.
  21. D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, ``Fabrication of a Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations for Greedy Power-Reduced Logic Applications," IEICE Electronics Express (ELEX), vol. 10, No. 23, pp. 20130772~1-20130772~10, Nov. 2013.
  22. D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu, ``A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure," Jpn. J. Appl. Phys. (JJAP), vol. 52, No. 4, pp. 04CM04~1-04CM04~6, Mar. 2013.
  23. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, ``Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic-Tunnel-Junction and Metal-Oxide-Semiconductor Hybrid Structure," Jpn. J. Appl. Phys. (JJAP), vol. 51, No. 4, pp. 04DM02~1-04DM02~5, Apr. 2012.
  24. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, ``Six-input Lookup Table Circuit with 62% Fewer Transistors Using Nonvolatile Logic-in-Memory Architecture with Series/Parallel-Connected Magnetic Tunnel Junctions," J. Appl. Phys. (JAP), vol. 111, issue 7, pp. 07E318~1-07E318~3, Feb. 2012.
  25. 鈴木大輔, 夏井雅典, 羽生貴弘, ``TMRロジックに基づくルックアップテーブル回路とその瞬時復帰可能FPGAへの応用", 電子情報通信学会論文誌C, vol. J92-C, no.7, pp.233-240, Jul. 2009.

国際学会 (査読有り)

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  1. D. Suzuki, T. Oka, and T. Hanyu, ``Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once-Write Shifting," Proc. IEEE 14th Int. Symp. Embedded Multicore/Many-core Systems-n-Chip (MCSoC2021), pp. 92-97, Dec. 2021.
  2. D. Suzuki, T. Oka, and T. Hanyu,``Design of an Energy-Efficient Nonvolatile-FPGA-Based BCNN Accelerator Using an Active-Load-Localized Single-Ended Circuit Style," Ext. Abst. 2021 Int. Conf. Solid-State Devices and Materials (SSDM 2021), pp.670-671, Sept. 2021.
  3. T. Oka, D. Suzuki, and T. Hanyu, ``Challenge of Energy-Efficient Edge-AI Hardware Using Spintronics-Based Nonvolatile Logic," 2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA 2020), pp. 85-88, Nov. 2020.
  4. Y. Takako, D. Suzuki, M. Natsui and T. Hanyu, "Systematic Design Flow for Realizing MTJ-Based Nonvolatile FPGAs," Ext. Abstr. 2020 Int. Conf. Solid-State Devices and Materials, pp. 93-94, Sep. 2020.
  5. D. Suzuki, T. Oka, and T. Hanyu, ``Design of an Energy-Efficient Binarized Convolutional Neural Network Accelerator Using a Nonvolatile FPGA with Only-Once-Write Shifting," Ext. Abstr. 2020 Int. Conf. Solid-State Devices and Materials (SSDM2020), pp. 91-92, Sep. 2020.
  6. D. Suzuki and T. Hanyu, ``Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA,” Proc. the 50th Int. Symp. Multiple-Valued Logic (ISMVL2020), pp. 194-199, May 2020.
  7. D. Suzuki and T. Hanyu, ``Design of an Energy-Efficient Controller for Realizing a Data-Shift-Minimized Nonvolatile FPGA," Ext. Abstr. 2019 Int. Conf. Solid State Devices and Materials (SSDM2019), pp. 525-526, Sep. 2019.
  8. M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu, ``An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz," 2019 IEEE International Solid-State Circuits Conference (ISSCC2019), pp. 202-203, Feb. 2019.
  9. D. Suzuki and T. Hanyu, ``A High-Read-Margin MTJ-Based Fracturable Lookup Table Circuit Using a Series-NMOS-Resistance-Reduced Logic-in-Memory Structure," Ext. Abstr. 2018 Int. Conf. Solid State Devices and Materials (SSDM2018), B-4-02, pp. 117-118, Sep. 2018.
  10. D. Suzuki and T. Hanyu, ``Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA," 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), pp. 291, Feb. 2018.
  11. D. Suzuki and T. Hanyu, ``Design of an MTJ-Oriented Nonvolatile Lookup Table Circuit with Write-Operation Minimizing," Ext. Abstr. 2017 Int. Conf. Solid-State Devices and Materials (SSDM2017), pp.195-196, Sep. 2017.
  12. T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui, ``Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor," Design, Automation & Test in Europe (DATE), pp. 548-553, Mar. 2017.
  13. D. Suzuki and T. Hanyu, ``A Self-Terminated One-Phase Write Driver for Complementary-MTJ Based Memory Cells," Abstr. 61st Annual Conference on Magnetism & Magnetic Materials (MMM), p. 554, Nov. 2016.
  14. D. Suzuki and T. Hanyu, ``A Self-Terminated Energy-Efficient Nonvolatile Flip-Flop Using 3-terminal Magnetic Tunnel Junction Device," Ext. Abstr. 2016 Int. Conf. Solid-State Devices and Materials (SSDM2016), pp. 911-912, Sep. 2016.
  15. D. Suzuki and T. Hanyu, ``A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure," Proc. Int. Conf. Field-Programmable Logic and Applications (FPL), pp. 1-4, Aug. 2016.
  16. D. Suzuki and T. Hanyu, ``Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 5-10, May 2016.
  17. D. Suzuki and T. Hanyu, ``Design of an MTJ-Based Nonvolatile Lookup Table Circuit Using an Energy-Efficient Single-Ended Logic-In-Memory Structure," Proc. IEEE 58th Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 317-320, Aug. 2015.
  18. D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, ``Fabrication of a 3000-6-Input-LUTs Embedded and Block-Level Power-Gated Nonvolatile FPGA Chip Using p-MTJ-Based Logic-in-Memory Structure," Symp. VLSI Circuits Dig. Tech. Papers, pp. 172-173, Jun. 2015.
  19. T. Hanyu D. Suzuki, N. Onizawa, S. Matsunaga, M. Natsui, and A. Mochizuki ``Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm," Proc. Design Automation & Test in Europe (DATE), pp. 1006-1011, Mar. 2015.
  20. T. Hanyu, D. Suzuki, A. Mochizuki, M. Natsui, N. Onizawa, T. Sugibayashi, S. Ikeda, T. Endoh, and H. Ohno, ``Challenge of MOS/MTJ-Hybrid Nonvolatile Logic-in-Memory Architecture in Dark-Silicon Era," IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp 28.2.1-28.2.3, Dec. 2014.
  21. D. Suzuki and T. Hanyu, ``MTJ-Based Low-Energy Nonvolatile Flip-Flop Using Area-Efficient Self-Terminated Write Driver," Abstr. 59th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 813, Nov. 2014.
  22. D. Suzuki and T. Hanyu, ``Nonvolatile FPGA Using 2T-1MTJ-Cell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic," Ext. Abstr. 2014 Int. Conf. Solid-State Devices and Materials (SSDM2014), pp. 450-451, Sep. 2014.
  23. D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, ``Optimally Self-Terminated Compact Switching Circuit Using Continuous Voltage Monitoring Achieving High Read Margin for STT MRAM and Logic," Abstr. International Magnetics Conference (INTERMAG), pp. 2506-2507, May 2014.
  24. D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu, ``Fabrication of a Perpendicular-MTJ-Based Compact Nonvolatile Programmable Switch Using Shared-Write-Control-Transistor Structure," Abstr. 58th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 233, Nov. 2013.
  25. D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, ``Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability," Ext. Abstr. 2013 Int. Conf. Solid-State Devices and Materials (SSDM2013), pp. 386-387, Sep. 2013.
  26. M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, ``Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating," IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 194-195, Feb. 2013.
  27. D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu, ``Design of Compact Nonvolatile Lookup-Table Circuit Using Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure," Ext. Abstr. 2012 Int. Conf. Solid State Devices and Materials (SSDM), pp. 392-393, Sep. 2012.
  28. D. Suzuki, M. Natsui, and T. Hanyu, ``Area-Efficient LUT Circuit Design Based on Asymmetry of MTJ's Current Switching for a Nonvolatile FPGA," Proc. 55th IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp. 334-337, Aug. 2012.
  29. L. Montesi, Z. Zilic, T. Hanyu, and D. Suzuki, ``Building Blocks to Use in Innovative Non-Volatile FPGA Architecture Based on MTJs," Proc. IEEE Computer Society Annual Symp. VLSI (ISVLSI), pp. 302-307, Aug. 2012.
  30. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, ``50%-Transistor-Less Standby-Power-Free 6-input LUT Circuit Using Redundant MTJ-Based Nonvolatile Logic-in-Memory Architecture," Abstr. 56th Annual Conf. Magnetism & Magnetic Materials (MMM), p. 480, Nov. 2011.
  31. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, ``A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure," Ext. Abstr. 2011 Int. Conf. Solid State Devices and Materials (SSDM2011), pp. 1464-1465, Sep. 2011.
  32. D. Suzuki, M. Natsui, H. Ohno, and T. Hanyu, ``Design of a Process-Variation-Aware Nonvolatile MTJ-Based Lookup-Table Circuit," Ext. Abstr. 2010 Int. Conf. Solid State Devices and Materials (SSDM2010), pp. 1146-1147, Sep. 2010.
  33. D. Suzuki, M. Natsui, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu, ``Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array," Symp. VLSI Circuits Dig. Tech. Papers, pp. 80-81, Jun. 2009.
  34. D. Suzuki, T. Endoh, and T. Hanyu, ``TMR-Logic-Based LUT for Quickly Wake-Up FPGA," Proc. 51st IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 326-329, Aug. 2008.